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Thoughts on IC development, EDA, and hardware design languages.

SystemVerilog Insights Series: Alias vs Assign … What’s the difference?

Posted by:Trent McClements | Posted on: August 24th, 2015 | 1 Comments

If you have used VHDL extensively, you probably know about the 'alias' declaration, but whether you have a VHDL or Verilog background, you may be surprised that the SystemVerilog LRM has also added an 'alias' construct that allows one physical net to have multiple names. I can hear the seasoned Verilog designers saying: 'What? That's crazy!... Why can't you just assign one net to another and be on your way?'. Well, that's a fair question and the answer is actually fairly intuitive, once you see it... (more…)

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Success: RTL level power/activity estimator in 48 Hours at DAC!

Posted by:Trent McClements | Posted on: July 22nd, 2015 | 2 Comments

If you recall from this post the Invionics team put on a 48 hour design challenge during DAC2015 (you may have read about the 48 hour challenge here). During the Monday morning of the conference we took suggestions for an EDA tool people would like to see developed. The suggestions were voted on by attendees during the day and then two of our Invionics developers had 48 hours to create the app based on our Invio EDA tool development platform. (more…)

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Invionics 48 Hour DAC Design Challenge

Posted by:Shawna Quinton | Posted on: June 1st, 2015 | 2 Comments

The developers at Invionics are ready to show the world how fast EDA App development can be with the Invio Platform. Invionics is holding a 48 hour EDA Development Challenge at the 52nd DAC. That's right. They are ready to, as they say, “eat their own dog food”. I have to admit, I'd never heard the term, but this is certainly not the only time I have wanted a Startup to English translation dictionary! (more…)

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Industry Insights: EDA Development Needs a 10X Productivity Improvement

Posted by:Brad Quinton | Posted on: May 13th, 2015 | 4 Comments

How long should it take to develop an EDA application? 2 years? 3 years? 4 years? You will rarely hear the answer in weeks or days, but that is exactly where it should be. Why? Because that is the current economic reality of software development. In EDA today, we seem to be slow to accept the new reality. As a result the software development world is passing us by. Hot-shot developers whip-off $100M SaaS businesses in a few months and we toil for years optimizing our pointer allocations in dark rooms.... (more…)

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EDA Tool Developer Series: What The Flop? … Part 3

Posted by:Trent McClements | Posted on: April 21st, 2015 | 1 Comments

In our previous two posts we gave a basic overview of flop detection and the anomalies that can occur in sensitivity lists. In this post we'll further discuss the subtlety of flop inference within an EDA tool, specifically looking at clocks and resets and how flop inference isn't solely based on sensitivity list analysis. (more…)

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EDA Tool Developer Series: What The Flop? … Part 2

Posted by:Trent McClements | Posted on: April 6th, 2015 | 3 Comments

Following on from our introductory discussion about flop detection in EDA tools, we'll look at the patterns that define a flip-flop, starting with a look at sensitivity lists. As we discussed in the last post, these patterns are not part of the VHDL, Verilog or SystemVerilog LRMs. They are conventional standards that the industry has evolved towards over time. To be an effective EDA developer, IC designer or verification engineer, it is important to understand how and why... (more…)

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Industry Insights: It is time for EDA to move to Python APIs

Posted by:Brad Quinton | Posted on: March 24th, 2015 | 7 Comments

When we started developing Invio we had a few goals we were aiming to hit. We wanted to help push forward EDA innovation by providing a base layer of HDL (Verilog, SystemVerilog, and VHDL) exploration and manipulation that was stable, intuitive, and (most importantly) easy to code to. We knew, as almost every EDA vendor out there knows, that without a Tcl API you might as well just pack your bags and go home. Tcl is just too ingrained in the mindshare of the semiconductor industry for an EDA vendor to not support it. So, we included a Tcl API. But, Tcl has it's limitations. It's not really meant for software development but rather it's strength lies in the end users ability to interact with it. True to its name, Tcl shines when used as a tool control language. So, then we were left with a choice. What language to develop an API used for serious software development? From our experience the answer was obvious: Python. (more…)

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EDA Tool Developer Series: What The Flop? … Part 1

Posted by:Trent McClements | Posted on: March 17th, 2015 | 2 Comments

The great innovation of HDL languages such as SystemVerilog and VHDL was to pull the designer out of thinking about gates and rather thinking functionality. This abstraction has enabled the extremely complicated ASICs and SoCs we see today. Most designers are comfortable with this abstraction in regards to combinational logic like adders, priority encoder/decoders and the like. But sequential elements are different. Hardware designers usually have something very specific in-mind for the sequential elements of their design. In that context it is interesting to consider that flip-flop and latch inference is left up to each specific EDA tool. Deviate from the simple case and things can be a lot more subtle than most people expect... (more…)

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Industry Insights: Excel is NOT an EDA tool!

Posted by:Brad Quinton | Posted on: February 25th, 2015 | 13 Comments

Nor is it a user interface. Nor is it a database. Excel is an accounting and numerical analysis tool, and a very useful one at that. However, I don't believe it is ever the right tool in an EDA design or verification flow (unless, of course, you are working on the budget!) As a former IC project manager, I don't know how many times I have sat down with a very clever engineer to see how they have automated some painful step in the development process, only to see some "unholy" collection of Perl (or Tcl, or SED) tied to CSV files and one or more manual steps using Excel. And my heart sinks. (more…)

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SystemVerilog Insights: Do always_latch and always_ff provide any real value?

Posted by:Trent McClements | Posted on: February 11th, 2015 | 5 Comments

On the surface they seem like fantastic extensions to the language, enabling designers to more explicitly state their design and guide verification and synthesis in a meaningful way. Gone are the days of inferring intent! We can now state and create what we want. But digging into the LRM, we can see that always_latch and always_ff may not provide the value you were expecting... (more…)

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