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Thoughts on IC development, EDA, and hardware design languages.

SystemVerilog: bet you didn’t know you could…(Part 2)

Posted by:Trent McClements | Posted on: November 16th, 2014 | 3 Comments

...have multiple different global domains (well, almost)!

Welcome to the world of SystemVerilog compilation units -- a deceptively simple concept. At first blush compilation units are like compile containers, or silos as I like to think of them, where a single file (single file compilation unit) or multiple files (multi-file compilation unit) can be compiled into. That seems pretty simple. The devil, however, is always in the details... First, the SystemVerilog LRM doesn't completely specify how compilation units are to be implemented so different tools may behave in different ways. Add to that the complications of things like macro definitions, packages, etc. and things get really interesting... We'll dive into that aspect in a later post. For today I just want to give an overview of just what the heck these compilation units things actually are! (more…)

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SystemVerilog: bet you didn’t know you could…(Part 1)

Posted by:Brad Quinton | Posted on: April 29th, 2014 | 4 Comments

SystemVerilog has been around for awhile now (after all, simple math shows it has been 9 years since the original 2005 standard, with years of committee work before that...). And, while it is now clear that it has become a completely mainstream design and verification language with support now coming from across the board in the EDA world and more recently even from the FPGA vendors (Altera Xilinx ), the language is large and complex. There is still a lot of interesting corners that are not so obvious to even the experienced hardware designer. (more…)

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