Thoughts on IC development, EDA, and hardware design languages.

EDA Tool Developer Series: What The Flop? … Part 1

Posted by: Trent McClements | Posted on: March 17th, 2015 | 2 Comments

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The great innovation of HDL languages such as SystemVerilog and VHDL was to pull the designer out of thinking about gates and rather thinking functionality. This abstraction has enabled the extremely complicated ASICs and SoCs we see today. Most designers are comfortable with this abstraction in regards to combinational logic like adders, priority encoder/decoders and the like. But sequential elements are different. Hardware designers usually have something very specific in-mind for the sequential elements of their design. In that context it is interesting to consider that flip-flop and latch inference is left up to each specific EDA tool. Deviate from the simple case and things can be a lot more subtle than most people expect…

When most people think about flops they think about a process with an edge-sensitive sensitivity list. Something like:

always @(posedge clk)
q <= d;

Or if they want an asynchronous reset, something like this:

always @(posedge clk or negedge rstb)
if (~rstb) q <= 1'b0;
else q <= d;

Of course, similar structures can also be used for latches (though obviously without the edge sensitivity). For these common patterns there is basic industry wide agreement on what defines a flip-flop or latch. We even went through and created an example of detection of standard flip-flop structures within RTL in the Simple Flop Detection Invio example. The important, and interesting, thing to note with this is that these standards are not part of the SystemVerilog LRM (nor VHDL LRM for that matter) but have arisen over time as common practice and thus it is left to your CAD tool or SystemVerilog parser to accommodate them. The SystemVerilog LRM did take a baby step towards defining a flop or latch structure with the always_latch and always_ff keywords but these don’t quite go the whole nine yards, as we discussed in this post.

At the heart of latch and flip-flop inference is patterning. Essentially all EDA tools look for HDL patterns that indicate that the designer wants a sequential element. For flip-flop the sensitivity list is the starting point. Through the sensitivity list we infer edge versus level (flop versus latch) structures and it helps us to infer sequential versus combinational logic. But, as we discussed in a previous post, sensitivity lists are not attached to always blocks but rather to statements themselves. This small fact opens up a range of possibilities on how to infer a sequential element, likely more ways than you would have guessed!

Over the next series of posts we’ll dissect numerous different ways to define flip-flops, latches, and RAMs. We will then compare these versus commonly used industry tools to see if we can define that blurry edge on what does and doesn’t infer a sequential element and which one is inferred. Do you have an example that tripped an EDA tool in that past? Or a suggested circuit you would like to see in our analysis? If you do, drop us a line and we will be sure to cover it of as we move through the series.


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Comments (2)

  1. Pingback: EDA Tool Developers Series: What The Flop? ... Part 2 - Invionics

  2. Pingback: EDA Tool Developer Series: What The Flop? ... Part 3 - Invionics - Invionics

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