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SystemVerilog Insights Series: Alias vs Assign … What’s the difference?

Posted by: Trent McClements | Posted on: August 24th, 2015 | 1 Comments

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If you have used VHDL extensively, you probably know about the ‘alias’ declaration, but whether you have a VHDL or Verilog background, you may be surprised that the SystemVerilog LRM has also added an ‘alias’ construct that allows one physical net to have multiple names. I can hear the seasoned Verilog designers saying: ‘What? That’s crazy!… Why can’t you just assign one net to another and be on your way?’. Well, that’s a fair question and the answer is actually fairly intuitive, once you see it…

The alias construct allows multiple names for the same net under the following conditions:

1) The nets must be of the same datatype
2) The nets must be of the same size
3) Alias statements cannot contain either variables nor hierarchical references

And all of those make sense. When aliasing one net to another net, given you are giving the same physical net a different name, the new name of the net must be defined to have the exact same size and be of compatible net type (i.e you can’t alias a tri0 to a tri1 net). Also, the scope of an alias is local so hierarchical references don’t make sense within that restriction.

OK, so that’s all relatively straight forward, but we haven’t really shown what an alias statement can do that an assign can’t. The SystemVerilog LRM points out one obvious example, and that’s shorting bidirectional nets. Say you wanted to short a bidir port, port1, to a second bidir port, port2. You can’t do this with a single assign statement since assignments are actually assigning the right-hand side of the statement to the left-hand side but not the inverse. So, the following is insufficient for bidir ports:

assign port1 = port2;

You can achieve the desired behaviour with an alias statement:

alias port1 = port2;

With the above line of code, the bidirectional aspect of both ports is preserved. You actually have shorted port1 to port2.

A nice side-effect of the alias command is that we can use it coupled to the .* or .name connection syntax shorthand (for more on that check out this blog post!). So, say you had two instances within your module, one of module mod0 and the other of mod1:

module mod0 (input clk, input rst, output out0);
...
endmodule

module mod1 (input clock, input reset, output out1);
...
endmodule

module mod2 (input c, input r, output o);
...
endmodule

module top (input clk, input reset, output out0, output out1, output out2);

mod0 mod0 (
.clk(clk),
.rst(reset),
.out0(out0));

mod1 mod1 (
.clock(clk),
.reset(rst),
.out1(out1));

mod2 mod2 (
.c(clk),
.r(rst),
.o(out2));

endmodule

Using alias you can change the above definition of the “top” module to the following:

module top (input clk, input reset, output out0, output out1);

alias clk = clock = c;
alias reset = rst = r;
alias out2 = o;

mod0 mod0 (.*);
mod1 mod1 (.*);
mod2 mod2 (.*);

endmodule

In the above code there are a couple of interesting and subtle things going on. First, the wires clock and rst are implicit nets and as such take the default net type (in this case wire). Second, the alias occurs on the implicit nets, clk and reset, created via the clk and reset port declarations of the top module. These two aspects allow the alias to exist without violating the three conditions for a SystemVerilog alias we listed above. In all, this is a nice way to clean up the code, assuming you’re comfortable with the .* and/or .name syntax (and your tool chain supports them!).

Have you ever used the alias statement in your code? I’d love to hear other usage cases and what worked as well as what didn’t in the comments below!

4-Ways-to-Build-Best-in-Class

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Comments (1)


  1. Yegor Hozbenko - Reply
    September 8, 2015

    In fact, comparing it to VHDL alias statement it is lightly different. First, in VHDL alias is declared in architecture before begin (not in a body of entity). Second, in VHDL alias statement allows you to give another name, for ex., to the slice of a vector which have different size. For ex.:
    signal phases_vec: std_logic_vector(3 downto 0) := (others => ’0′);
    –Phases aliases
    alias idr: std_logic is phases_vec(phases_position(IDR));

    Here intial signal is 4-bits, but alias is 1-bit. So, it is used just to have convinient naming and more readable code.

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